Operating Systems, Fall 2006, Homework 2
This homework will be covered in practise session on Thursday 14.9.2006 (week 37).
The homework and practice sessions will follow the normal department's practise. The homework is solved and done in advance, that is before the practise session. You may solve the problems alone or in a small group. The practise session is used to discuss about different solutions.
There should be also some time available for the team's to process their team tasks during the allocated time slot.
The exercises are based on chapters 1 and 2.
- Interrupts, I/O
- What happens if a device interrupt (I/O interrupt) occurs but device interrupts are disabled? How can this problem be avoided? Why would one want to disable device interrupts?
- What trouble would it cause, if the processor would not be able to recognize I/O interrupts? Could one build a processor like this and for what purpose?
- Problem 1.8 [Stal05] (Probl. 1.8 [Stal01]) ("Problem", not "Review Question"!)
- Cache and TLB
- Problem 1.13 [Stal05] (Probl. 1.13 [Stal01])
- How does the situation change, if we consider also virtual memory
address translation and TLB?
Assume that address translation is done according to the Figure 8.8 [Stal05] (Fig. 8.8 [Stal01]) before cache access. TLB hit ratio is 99% and the page table is found in main memory with 95% probability. TLB has the same speed as cache.
- Scheduling
- Problem 2.3 [Stal05] (Probl. 2.4 [Stal01]) from the text book (higher level answers, no details)
- How do scheduling policies for optimizing real time systems differ from those for time sharing and multiprogramming systems.
- Locality
- Problem 1.10 [Stal05]
- What other examples could you create about temporal locality?
- What about spatial locality?
- Problem 1.10 [Stal05]