On Sun, 25 May 2003, David S. Miller wrote:
> flush_dcache_page() or some architecture level equivalent belongs
> whereever the kernel uses CPU store instructions to modify a page's
> contents.
>
> When IDE uses PIO to do a data transfer, the flush belongs there.
> Right now this is occuring in the architecture defined IDE insw/outsw
> macros. It very well might be more efficient to do this at a higher
> level where the total extent of the I/O is known.
I'd prefer not to do this at driver level at all and rather let the user
of the data do it. The driver doesn't know how this page will be used, so
it has to assume the worst case.
E.g. for normal read calls there isn't a cache flush needed after a PIO
transfer and if the page is mapped nonexecutable, there is no page flush
needed either for physical caches.
It's also not just IO, a normal write call will dirty the page as well, so
before we map a page into userspace it's IMO the best time to synchronize
the caches. update_mmu_cache() might be a bad place for this as this is
called after set_pte().
bye, Roman
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