Re: SMP P4 APIC/interrupt balancing

[Dave Olien]

Cache warmth in handling interrupts is good.  In fact, this is one
of the reasons to use interrupt affinity.

But, directing all interrupts to single processor penalizes unfairly any
tasks that are scheduled to run on that processor.  Under heavy interrupt
load, a tasks can become effectively "pinned" onto that processor, unable
to get cpu time to make progress, and unable to be scheduled somewhere
else.

Under really heavy interrupt load, it's good to have
many processors handling interrupts.  It increases rate the system
can handle interrupts, and it reduces the latency of individual interrupts.

Dave.

> From [e-mail] Thu Apr 18 09:11:22 2002
> Date: 	Thu, 18 Apr 2002 12:04:35 -0400 (EDT)
> From: Bill Davidsen <[e-mail]>
> To: James Bourne <[e-mail]>
> cc: Linux Kernel Mailing List <[e-mail]>,
>    Ingo Molnar <[e-mail]>
> Subject: Re: SMP P4 APIC/interrupt balancing
> 
>   Is this positive or negative on performance? If you have a system
> getting so many interrupts that one CPU can't handle them, obviously there
> is a gain. However, by thrashing the cache of all CPUs instead of just one
> you have some memory performance cost.
> 
>   I first looked at this for a mainframe vendor who decided that putting
> all the interrupts in one CPU was better. That was then, this is now, but
> I am curious about metrics, like real and system time doing a kernel
> compile, etc.
>