It is expected. inter-APIC message got finally so damaged that
checksum was OK, but IRQ trap vector got mangled from 99 -> 8d
(I bet that it was 99->8d, as both have same checksum, and 99 could
be used...). So local APIC confirmed reception of 8d interrupt,
but 8d interrupt was never requested by IOAPIC :-( So 8d confirmation
is droped into wastebasket, but 99 IRQ is still marked as serviced
in IOAPIC, but never seen/EOIed by CPU.
For such motherboard you have two choices: (1) do not use IOAPIC at all
(when LINT#0/#1 are used in 8259 mode, they are not so sensitive to
electrical noise) or (2) apply another (frank's?) patch which resets IRQ
line every few seconds. Maybe hooking this reinitialization into NE2K
timeout hook... Or into userspace daemon when received packets does not
climb up for couple of seconds...
I think that on BP6 hardware there is no way around except using 'noapic',
or passing board through Abit replacement program. There is only two bit
checksum which guards 8 or 22 data bits. I have no idea how frequent two
bits errors are, but, as your example shows, they definitely happen on
your hardware.
Best regards,
Petr Vandrovec
vandrove@vc.cvut.cz
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