> > Having a reverse mappings is the least sucky way to handle virtual aliases
> > of certain types of MIPS caches.
>
> Hmm. I would think that increasing the logical page size in the kernel would
> be the trivial way to handle virtual aliases. (i.e.) with a large enough page
> size you can't actually have a virtual alias.
That's a possible solution; I'm not clear how bad the overhead would be.
Right now a virtual alias is a relativly rare event and we don't want the
common case of no virtual alias to make pay a high price. Or?
> You could also play some games with simply allocating pages only with the
> proper proper high bits. These games might also be useful on architectures
> for L2 caches who have significant physical bits than PAGE_SHIFT bits.
An alternative but less efficient solution. I tried to implement it; I ran
into problems with running out of larger pages soon as I had to split order 2
pages into 4 order 0 pages to implement this; the fragmentation was _really_
bad.
> But how does a reverse mapping help to handle virtual aliases? What are those
> caches doing?
You leave only mappings of one color accessible. All other mappings are made
unaccessible in the page table, so accessing will result in a TLB fault.
The TLB fault handler then flushes the active mappings, makes them
unaccessible by clearing the MIPS hw dirty / accessible bits, then makes the
mapping of the new color accessible in the page table. This is already
possible right now but doing the necessary reverse mappings can be rather
inefficient as is.
> The only model in my head is having a virtually indexed cache where you
> have more index bits than PAGE_SHIFT bits.
Which is exactly what many MIPS implementations are suffering from. At
least they're tagged with the physical address, so no flushes on context
switch necessary.
Ralf
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