Computer Organization II, Spring 2009, Exercise 3
These homework exercises will be covered in practice session on week 13 (In Finnish Thu 26.3., In English Fri 27.3).
Each week one article-based questions must be submitted on paper to the teacher.
You need (at least to try hard) to solve the questions in advance, that is before the meeting. In the meeting we will discuss about the questions and their solutions. There is no time to solve them there. Solutions to the homework are not provided afterwards.
This third week's homework covers digital logig, cache and memory.
ARTICLE:
Return the answer on paper in the meeting.
Look at the article: L. Peng et.al.: Memory hierarchy performance measurement of commercial dual-core desktop processors. Journal of Systems Architecture 54(2008) 816-828. (publisher Elsevier)
The article is based on measuring performance differences of three commercial processors.
Please write (In Finnish or in English) a short (1/2 -1 page) review of the paper. Please focus in your review in such questions as
- Which of the processor was best and why?
- Name also at least one situation where one of the others was better and explain why.
- At the end explain based on this article what kind of architecture features would you recommend for a boss, friend or small company and why. Please do not just pick one of the processors, but try to list more general features.
HOMEWORK:
- Problems B.4 and B.6 [Stal06, p.
731];
(A.4, A.6 [Stal03]) (A.4, A.6 [Stal99])
- Problem B.8
[Stal06]
(A.8 [Stal03]) (A.8 [Stal99])
Parts a) and b) - Problem B.8
[Stal06]
(A.8 [Stal03]) (A.8 [Stal99])
Part (d): Give a Karnaugh map for SOP presentation of Z1, and use it the get an optimized SOP presentation for Z1.
- Problem
4.9 [Stal06]
(4.8
[Stal03]) (4.14 [Stal99])
Give also an example on situation where the approximation does not work (I.e., cache line A is replaced even though line B was referred to longer time ago). Why does it not work? - Problems 4.5 and 4.23
(4.4 [Stal03]) )
Problem 4.23 is not in the earlier editions:
Consider a cache with a line size of 64 bytes. Assume that on average 30% of the lines in the cache are dirty. A word consists of 8 bytes.- Assume there is a 3% miss rate (0.97 hit ratio). Compute the amount of main memory traffic, in terms of bytes per instruction for both write-through and write-back policies. Memory is read into cache one line at a time. However, for write back, a single word can be written from cache to main memory.
- Repeat part a for a 5% rate.
- Repeat part a for a 7% rate.
- What conclusion can you draw from these results?
Self-study:
If you feel that you would like to have more exercise with the memory addressing and set-associative cache, please follow the link. I have created a simple set of questions, that hopefully help you in understanding the address handling in set-associative cache.