Extra: Memory addresses and set-associative cache
This exercise is just created just for fun. If you feel that you need more practise with memory addressing, please feel free to do this task. If you are not able to follow some part, please contact the lecturer.
- Memory
- Let us assume that the computer has only 32 addressable memory locations. How many bits are needed for addressin? Draw the memory and write down all addresses in binary format for each memory cell.
- Cache
- We have also very small cache.
- Let us assume that each cache line has two of the memory locations. How many bits are needed in the offset to distinguish these two addresses?
- Let us assume that we have two-way set associative cache. Each set can then store two of the cache lines. If we assume that the cache has four sets, how many bits are needed for the set information? How many bits are then left for the tag?
- Playing around
- Now you have your memory and cache available. Fill your memory with some data (use letters for example)
- The start with your cache empty. Make memory accesses in the order: x02, x12, x08, x03, x0B, x0A. The addreses are given in hexadecimal format. (If I did not have mistakes in the sequence, you should have ended up with two cache hits and one replacement.)
- Enhancing
- How would the situation change, if you increase the memory size to 64 items?
- Whst if you increase the cache size to eight?
- What if you use four-way set-associative cache?
- How can you handle the situation, where you want to expand the system in such a way that you split each memory location (word) to bytes and make each byte addressable? Keep the cache line size (in bits) the same.
- Suggestions for improvement
- Please send me comments about this task and ideas how to improve it for your benefit.