8 bits
3 2
3
16 bits
I------------------I----I-----I-----I----------------------------I
I
I I
I
I
I
I Instruction code
I J I
M I
I I address
part ADDR
I
I----------------- I -- - I-----I-----I----------------------------I
31 24 23 16 15 0
In symbolic machine language instructions are displayed in the following form:
REFERENCE OPER Rj,M ADDR(Ri)
where OPER the symbolic name of the instruction
Rj
the 1st operand (register R0..R7)
M
addressing mode:
= direct operand
direct addressing (empty, is not entered)
@ indirect addressing
ADDR address
part (memory address or constant)
Ri
possible index register (register R0..R7)
If one part of the instruction is not significant, it can be left out.
The instruction can be preceeded by a symbolic address as a reference,
and
it must contain at least one character other than a number.
Legal characters are A-Z, 0-9 and _. Only the first 8 characters are
significant.
The following forms are available for almost all instructions :
OPER Rj,ADDR
direct memory addressing
OPER Rj,Ri
direct register addressing
OPER Rj,=ADDR immediate
operand
OPER Rj,@ADDR indirect
memory addressing
OPER Rj,ADDR(Ri) indexed addressing
OPER Rj,=ADDR(Ri) indexed immediate addressing
OPER Rj,@ADDR(Ri) indexed indirect memory
addressing
Exceptions:
STORE
the 2nd operand is always destination address, it can't
be a register or a constant
POP
the 2nd operand must always be a register
PUSHR
the 2nd operand is not significant
POPR
the 2nd operand is not significant
BRANCHING-
the 2nd operand is always destination address, it can't
INSTRUCTIONS be a constant. the
1st operand is not significant with
instructions that examine the state register
NOP operands are not significant
======================================================================
TTK-91 symbolic machine language instructions
======================================================================
Data transfer instructions:
LOAD
takes the value of the 2nd operand and makes it the new value of
register Rj.
STORE
stores an integer in register Rj as the value of the 2nd operand.
IN
reads an integer to register Rj from a peripheral appointed in the 2nd
operand (from keyboard for example IN R1,=KBD)
OUT
prints an integer from register Rj to the peripheral appointed in the
2nd operand (to screen for example OUT R1,=CRT)
Arithmetic ja logic instructions:
ADD
(add) add the value of the 2nd operand to the value in register Rj.
SUB
(subtract) substract the value of the 2nd operand from the value
in register Rj.
MUL
(multiply) multiply the value in Rj by the the 2nd operand.
DIV
(divide) divide the value in register Rj with the 2nd operand.
In division only the modulus is significant.
MOD
(modulo) divide the value in register Rj with the 2nd operand.
In division only the remainder is significant.
AND
(boolean AND) logical AND-operation.
OR
(boolean OR) logical OR-operation.
XOR
(boolean XOR) logical exclusive OR-operation.
SHL
(shift left) shift register Rj's bits left the amount stated in
the 2nd operand. Fill the right end with 0-bits.
SHR
(shift right) like SHL, but shift right.
COMP
(compare) compares the value of the 1st operand to the value of the
2nd operand and sets the result of the comparison to the bits of
state register SR
L=less, E=equal, G=greater.
Branching instructions:
JUMP
(unconditional jump) unconditional jump to the target address
stated in the 2nd operand.
JNEG
(jump if negative) if Rj < 0, jump to the address stated in the
2nd operand, otherwise continue from the next instruction.
JZER
(jump if zero) if Rj =
0
JPOS
(jump if positive) if Rj > 0
JNNEG (jump if
not negative) if Rj >= 0
JNZER (jump
if not zero) if Rj <> 0
JNPOS
(jump if not positive) if Rj <= 0
JLES
(jump if less) if the state register SR's bit L is set, jump to the
address stated in the 2nd operand, otherwise continue from the next
instruction (used with the COMP-instruction).
JEQU
(jump if equal) if bit
E is set
JGRE
(jump if greater) if bit G is set
JNLES
(jump if not less) if bit E or G is set
JNEQU (jump
if not equal) if bit L or G is set
JNGRE (jump
if not greater) if bit L or E is set
Stack instructions:
The first operand of the instruction, Rj, points to the cell on top
of the stack.
Usually the register SP (ie R6) is used as stack pointer.
PUSH Increase
the value of stack pointer Rj by one and store the 2nd operand as
the top cell of the stack.
POP
Remove the top cell from stack and take it to the register stated in the
2nd operand (NOTICE: always a register).
Reduce the value of stack pointer Rj by one.
Subroutine instructions:
CALL (call procedure)
a subroutine call, ie transferring the control
to the address stated with the 2nd operand. Stores the return address
in stack, to which' top Rj is pointing.
EXIT
returns from a subroutine to the next instruction. The return address is
found from stack, to which' top Rj is pointing. The 2nd operand is the
number of the parameters transmitted in stack.
System calls:
SVC
(supervisor call) A call for a operanting system's service routine.
(system call). The first operand is the top of the stack Rj and the
second operand is the number of the service.
Service numbers:
HALT : Ends program
execution.
TIME : Gives
the time. Addresses transmitted with stack, where
the hours, minutes and seconds are desired. (NOTICE: order!).
DATE : Gives
the date. Addresses transmitted with stack, where
the day, month and year are desired. (NOTICE: order!).
READ :
Reads an integer. Address transmitted with stack, where the
integer is desired to be read.
WRITE: Writes
an integer. A printable value transmitted with stack.
Other:
NOP (no operation)
======================================================================
TTK-91 machine language instruction codes
======================================================================
Instruction Code Decimal Hexdecim.
NOP 0000 0000 0 00
STORE 0000 0001
1 01
LOAD 0000
0010 2
02
IN
0000 0011 3
03
OUT
0000 0100 4
04
ADD
0001 0001 17
11
SUB
0001 0010 18
12
MUL
0001 0011 19
13
DIV
0001 0100 20
14
MOD
0001 0101 21
15
AND
0001 0110 22
16
OR
0001 0111 23
17
XOR
0001 1000 24
18
SHL
0001 1001 25
19
SHR
0001 1010 26
1A
COMP 0001 1111 31 1F
JUMP 0010
0000 32 20
JNEG 0010
0001 33 21
JZER 0010
0010 34 22
JPOS 0010
0011 35 23
JNNEG 0010 0100
36 24
JNZER 0010 0101
37 25
JNPOS 0010 0110
38 26
JLES 0010
0111 39 27
JEQU 0010
1000 40 28
JGRE 0010
1001 41 29
JNLES 0010 1010
42 2A
JNEQU 0010 1011
43 2B
JNGRE 0010 1100
44 2C
CALL 0011
0001 49 31
EXIT 0011
0010 50 32
PUSH 0011
0011 51 33
POP
0011 0100 52
34
SVC
0111 0000 112 70
IRET 0111
0001 113 71
======================================================================
Compiler control instructions (fake instructions)
======================================================================
The compiler control instructions give instructions to the assembler's
compiler. They ARE NOT actual instructions of the assembler.
label EQU value
The equation instruction EQU defines an integer value to a symbolic
label.
The label can be used in an instruction's ADDR-field, after which it
will
be handled like a "value" typed in the same place.
label DC value
Memory allocation instruction DC (data constant) reserves one memory
word
for a constant, equates the address of the allocated memory cell and
the
symbolic address "label" and sets the number "value" as the contents
of
the reserved memory cell. The label can be used in an instruction's
ADDR-
field like a memory address.
label DS size
The data reservation instruction DS (data segment) allocates a memory
block
which's size is "size" (as words) and equates the starting address
of the
allocated memory cell and the symbolic address "label". Is used for
allocating space for global variables. A label can be used in an instruction's
ADDR-field like a memory address.