Computer Organization II,  Autumn 2006, HW 3

1. Problems B.4 and B.6 [Stal06, p. 731]             (A.4, A.6 [Stal03]) (A.4, A.6 [Stal99])

2. [2 HWP] Problem B.8 [Stal06]                       (A.8 [Stal03]) (A.8 [Stal99])
   NOTE: overall picture and details for Z1 only.
   Part (d): Give a Karnaugh map for SOP presentation of Z1, and use it the get an optimized SOP presentation for Z1.
   
   
3. Problem 4.9 [Stal06]                         (4.8 [Stal03]) (4.14 [Stal99])
   See also Fig 4.15.pdf [Stal06 tai Stal03].
   Give an example on situation where the approximation does not work (I.e., cache line A is replaced even though line B was referred to longer time ago). Why does it not work?

4. Processor has a unified write back cache. Its hit ratio is 98%. Each instruction has, in average, 1.4 memory references (instruction plus 0.4 data references). Cache line is 4 words. There is bus transaction with which one can read or write whole cache line in 50 clock cycles (CPU cycles). To read or write one word takes 30 clock cycles. About 20% of the cache blocks have been written onto. To execute one instruction it takes in average 5 clock cycles plus the time for those data items that are not found in cache. During a cache miss the processor is waiting. The processor executes one instruction at a time.  
   1. How many clock cycles per instruction is needed, in average, for this processor?
   2. How many clock cycles per instruction would be needed, in average, for this processor, if there were no cache?