Homework
Computer Organization II, Autumn 2006, HW 2
This will be covered in practise session during the week 37 (11-15.9.2006)- Hardware support for operating system. It is difficult to make a reliable operating system (such that the applications can not disturb each other or use other's resources without permission), if one does not get some (processor) hardware support for it. What types of services (support) does the processor hardware offer for this purpose
- in memory management?
- in process management?
- in device management?
- in resource managament?
- I/O.
- Explain term memory-mapped I/O and how is it implemented? What would be an alternative for it?
- What does DMA mean and how is it implemented? What would be an alternative for it?
- Problems 3.9 and 3.19 [Stal06] (3.8, 3.10 [Stal03]) (3.7, 3.9 [Stal99])
- Problem 3.8 [Stal06]
(3.7 [Stal03]) (3.6 [Stal99])
- How does one prevent two devices to act simultaneously as Bus Masters, when they both try to use the bus at the same time? Who makes the decision? Which device (or devices) get the turn? How does one know that it got the turn?
- What determines, how many devices can be attached to the bus?
- PCI-bus.
- Assume that the memory circuit can locate the target data in one, two
or 3 clock cycles. How does the memory circuit tell this to the CPU?
See Fig 3.23 [Stal06] (Fig 3.23 [Stal03]) (Fig 3.22 [Stal99]) - Assume that the last data set has only 1 byte of data even though the data bus is 32 bits wide. Who determines which 8 wires are used to transmit that byte? When and how that information is given to the other party?
- What happens if three devices want simultaneously use the bus? Who makes the decision? Which device (or devices) get the turn? How does one know that it got the turn? Will signals get crossed, when all devices have the REQ-pin at the same location?
- Assume that the memory circuit can locate the target data in one, two
or 3 clock cycles. How does the memory circuit tell this to the CPU?
Teemu Kerola