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Computer Organization II,  Fall 2002, HW 1

1. I/O.
   1. Explain term memory-mapped I/O?
   2. What other possibilities are there to implement I/O than memory-mapped I/O?
   3. Why would memory mapped I/O be better than its alternative(s)?
   4. How can one implement a system where user level processes can not mess up data structures used in memory mapped I/O, by accident or in purpose? Give at least two possible solutions.
      
      
      
2. User state and priviledged state
   1. Give three different types of situations where processor state changes from user state to priviledged state.
   2. Give an example of a situation where processor state does not change to user state at the time of interrupt handler return.
   3. What use is there from the priviledged state? What bad?
   4. Would it be useful to offer multiple levels of priviledged states? Why?

    

3. Problems  3.8 and 3.10 from text book [Stal03, p. 92]    (probl. 3.7 and 3.9 [Stal99, p. 91]).
   

    

4. Problem 3.7 from text book [Stal03, p. 91]                 (probl. 3.6 [Stal99, p. 91])
   1. How does one prevent two devices to act simultaneously as Bus Masters, when they both try to use the bus at the same time? Who makes the decision? Which device (or devices) get the turn? How does one know that it got the turn?
   2. What determines, how many devices can be attached to the bus?

    

5. PCI-bus.
   1. Assume that the memory circuit can locate the target data in one, two or 3 clock cycles. How does the memory circuit tell this to the CPU? (see Fig 3.23 [Stal03] or Fig 3.22 [Stal99]))
   2. Assume that the last data set has only 1 byte of data even though the data bus is 32 bits wide. Who determines which 8 wires are used to transmit that byte? When and how that information is given to the other party?
   3. What happens if three devices want simultaneously use the bus? Who makes the decision? Which device (or devices) get the turn? How does one know that it got the turn?