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581365-8 Computer Organization II, Final exam 27.3.2007  

Write in each answer sheet your name, signature, id-number, course name, and page nr/total nr of pages.

1. [18 p] Dependencies. Assume that RISC architecture ALU instructions have three register operands and that the result is stored into the first (left-most) register. The architecture is implemented in ordinary (not superscalar) pipelined fashion so that, in best case, one instruction can be completed in each cycle. The pipeline has 5 phases (instruction fetch, instruction decode, register read, ALU, write back).
   
   Observe the following set of instructions generated by the compiler (instruction number on left):

   1         Load  R2, VarX     ; Regs(2) <- Mem(VarX)
   2         Add   R5, R5, R2   ; Regs(5) <- Regs(5) + Regs(2)  
   3 Loop    Move  R2, R6       ; Regs(2) <- Regs(6)
   4         Add   R3, R3, R2
   5         Add   R2, R3, R5 
   6         Jnzer R3, Loop
   7         Move  R1, R2

   Many aspects in the preceding code segment may reduce the execution speed from the maximum possible.
   1. Describe precisely the problem types defined below and mark in a clear way one occurrence of each problem type in the preceding code segment (if it appears there):
      • data dependency
      • control dependency
      • structural dependency
      How can one avoid or reduce the performance problems caused by each problem type?  
       
   2. How can one avoid the problems or reduce the performance effects caused by data, control or structural dependencies? Give one solution to each dependency type and describe shortly how it works.
      
   3. Assume now, that the architecture is implemented as superscalar with fetch policy fetch and decode 3 instructions at a time and issue policy out-of-order issue, out-of-order completion. Describe precisely new dependency types given below and mark in a clear way one occurrence for each problem type in the preceding code segment (if it appears there).
      • output dependency
      • antidependency
        
   4. How can one avoid the problems or reduce the performance effects caused by these new dependency types given in part (c)? Give one solution to each new dependency type and describe shortly how it works.

       Make all needed assumptions and write them down.

2. [9 p] Virtual memory
   1. How do virtual memory TLB and cache work together to minimize the time spent for memory references?
   2. What is there common with TLB and cache?
   3. What are the biggest differences betwen TLB and cache?
   4. Is temporal locality taken advantage of in TLB and in cache? How does it show?
   5. Is spatial locality taken advantage of in TLB and in cache? How does it show?
       
       
3. [9 p] IA-64 and Itanium. Explain the following IA-64 architecture concepts. Give a (machine language level) example to each one.
   1. WLIW, bundle, template
   2. Predicated execution
   3. Speculative loading (control speculation)
   4. Data speculation
   5. Software pipelining