581365-8 Computer Organization II, course exam 2.11.2001

Write in each sheet of paper: your name and signature, student id, course name, and page number.

  1. [12 p] Combinatorial circuit is used to control a 7-segment display (see Figure A.34). The circuit has four inputs, which represent a packed coded decimal number. So, numbers  0, 1, 2,..., 9 are coded into bits 0000, 0001, 0010, ..., 1001. The input bits are from left to right order X1, X2, X3, X4. (If you want, you can rename them to A, B, C and D)

    Based on the input, the circuit determines which display segments will be activated (lit). We now concentrate only on display segment Z5 (vertical line, left, bottom) and the output pin Z5 controlling it. The value of output pin Z5 is one (1) when that segment is lit.

    1. [3 p] Give  Z5 as a truth table.
    2. [3 p] Give Z5 as a Boolean statement in SOP (sum of products) form.
    3. [3 p] Give the SOP form Karnaugh map of Z5 and the simplest possible SOP-form boolean statement for Z5. Show how the simplification was done with Karnaugh map.
    4. [3 p] Give Z5 as a Boolean statement in POS (product of sums) form.

  2. [12 p] Virtual memory
    1. [2 p] What is the basic problem solved by virtual memory?
    2. [2 p] What phenomena is the solution based on?
    3. [3 p] What does TLB has to do with the basic problem? Which problem is solved with TLB? What use is there with TLB?
    4. [3 p] What is there common with TLB and cache? How do they differ?
    5. [2 p] What is inverted page table and what is good/bad with it as compared to ordinary page table?

  3. [12 p] Dependencies. Assume that RISC architecture ALU instructions have two register operands and that the result is stored into the first (left-most) register. The architecture is implemented in ordinary (not superscalar) pipelined fashion so that, in best case, one instruction can be completed in each cycle.

    Observe the following set of instructions generated by the compiler: 
    	Load	R2, VarX   ; Regs(R2) <- Mem(VarX)
	Add	R5, R2     ; Regs(R5) <- Regs (R5) + Regs(R2)  
	Load	R2, VarY
	Add	R3, R2
	Mul	R3, R5
	Jnzer	R2, Loop
	Add	R4, R2
    Many aspects in the preceding code segment may reduce the execution speed from the maximum possible for that architecture.
    1. [8 p] Describe precisely the problem types defined below and mark in a clear way all occurrences of each problem type in the preceding code segment:
      • data dependencies
      • structural dependencies
      • control dependencies
      How can one avoid or reduce the performance problems caused by each problem type?

       

    2. [4 p] Assume now, that the architecture is implemented as superscalar. Describe precisely new problem types given below and mark in a clear way all occurrences for each problem type in the preceding code segment.
      • output dependencies
      • antidependencies
      How can one avoid or reduce the performance problems caused by each new problem type?

        Make all needed assumptions and write them down.

  4. [12 p] Hardwired control.
    1. [3 p] What problem is solved by (hardwired) control?
    2. [3 p] How does hardwired control work? Give an example (with a picture).
    3. [2 p] What problemns are there in hardwired control as compared to microprogrammed control?
    4. [2 p] What advantages are there in hardwired control as compared to microprogrammed control?
    5. [2 p] Would it be advisable to implement a RICS processor with hardwired or microprogrammed control? Why?