[PATCH 2.5.72 1/2] i_size atomic access

Daniel McNeil (daniel@osdl.org)
19 Jun 2003 11:16:56 -0700


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This adds a sequence counter only version of the reader/writer
consistent mechanism to seqlock.h This is used in the second
part of this patch give atomic access to i_size.

re-diff against 2.5.72.

The patch is also available for download from OSDL's patch lifecycle
manager (PLM):

http://www.osdl.org/cgi-bin/plm?module=patch_info&patch_id=1939

Daneil McNeil <daniel@osdl.org>

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diff -rupN -X /home/daniel_nfs/dontdiff linux-2.5.72/include/linux/seqlock.=
h linux-2.5.72-isize/include/linux/seqlock.h
--- linux-2.5.72/include/linux/seqlock.h 2003-06-16 21:20:00.000000000 -070=
0
+++ linux-2.5.72-isize/include/linux/seqlock.h 2003-06-17 16:56:25.15995628=
9 -0700
@@ -94,6 +94,57 @@ static inline int read_seqretry(const se
return (iv & 1) | (sl->sequence ^ iv);
}
=20
+
+/*
+ * Version using sequence counter only.=20
+ * This can be used when code has its own mutex protecting the
+ * updating starting before the write_seqcntbeqin() and ending
+ * after the write_seqcntend().
+ */
+
+typedef struct seqcnt {
+ unsigned sequence;
+} seqcnt_t;
+
+#define SEQCNT_ZERO { 0 }
+#define seqcnt_init(x) do { *(x) =3D (seqcnt_t) SEQCNT_ZERO; } while (0)
+
+/* Start of read using pointer to a sequence counter only. */
+static inline unsigned read_seqcntbegin(const seqcnt_t *s)
+{
+ unsigned ret =3D s->sequence;
+ smp_rmb();
+ return ret;
+}
+
+/* Test if reader processed invalid data.
+ * Equivalent to: iv is odd or sequence number has changed.
+ * (iv & 1) || (*s !=3D iv)
+ * Using xor saves one conditional branch.
+ */
+static inline int read_seqcntretry(const seqcnt_t *s, unsigned iv)
+{
+ smp_rmb();
+ return (iv & 1) | (s->sequence ^ iv);
+}
+
+
+/*=20
+ * Sequence counter only version assumes that callers are using their
+ * own mutexing.
+ */
+static inline void write_seqcntbegin(seqcnt_t *s)
+{
+ s->sequence++;
+ smp_wmb(); =09
+}=09
+
+static inline void write_seqcntend(seqcnt_t *s)=20
+{
+ smp_wmb();
+ s->sequence++;
+}
+
/*
* Possible sw/hw IRQ protected versions of the interfaces.
*/

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