Re: problem with Serverworks CSB5 IDE

[Duncan Laurie]

Alan Cox wrote:
> On Gwe, 2003-04-25 at 17:39, Duncan Laurie wrote:
> 
>>mode because the PCI interrupt pin register is hardwired to zero (don't
>>ask me why...) so it follows a codepath in do_ide_setup_pci_device()
>>where init_chipset isn't called.
> 
> 
> That would imply a problem in the PCI layer, since the IRQ should have 
> been assigned, and if the IRQ is not assigned we can't use the device.
> 
> I'll take a look. 
> 

It might just be another unfortunate serverworks chipset bug...

The CSB5 doesn't appear to fully support native mode--sure you can
put it in native mode (!) and you're free to assign the BARs any
way you want, but it still assumes IRQ14 for ide0 and IRQ15 for
ide1 when they should really be collapsed and shared on a single
PCI (non-compatibility) interrupt.

While it might be possible to re-route the interrupts using the
pirq table and a few different bits in the southbridge, that still
wouldn't solve the problem of PCI config reg 0x3c being read-only
and set to zero in the IDE function..

The best answer might be to not use native mode.  We can force it
into legacy mode with a pci quirk and it works, but its ugly:

--- quirks.c~   2003-04-25 11:37:46.000000000 -0700
+++ quirks.c    2003-04-25 11:46:45.000000000 -0700
@@ -631,6 +631,22 @@
                 interrupt_line_quirk = 1;
  }

+/*
+ *     Serverworks CSB5 IDE does not fully support native mode
+ */
+static void __init quirk_svwks_csb5ide(struct pci_dev *pdev)
+{
+       u8 prog;
+       pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
+       if (prog & 5) {
+               prog &= ~5;
+               pdev->class &= ~5;
+               pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
+               /* need to re-assign BARs for compat mode */
+               quirk_ide_bases(pdev);
+       }
+}
+
  /*
   *  The main table of quirks.
   */
@@ -702,6 +718,8 @@

         { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_CYRIX,    PCI_DEVICE_ID_CYRIX_PCI_MASTER, 
quirk_mediagx_master },

+       { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_SERVERWORKS, 
PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide },
+
  #ifdef CONFIG_X86_IO_APIC
         { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_AMD,      PCI_DEVICE_ID_AMD_8131_APIC,
           quirk_amd_8131_ioapic },

-duncan