Re: [Bug 350] New: i386 context switch very slow compared to 2.4

[george anzinger]

H. Peter Anvin wrote:
> Followup to:  <[e-mail]>
> By author:    Linus Torvalds <[e-mail]>
> In newsgroup: linux.dev.kernel
> 
>>Wow. There aren't many things that AMD tends to show the P4-like "big
>>latency in rare cases" behaviour.
>>
>>But quite honestly, I think they made the right call, and I _expect_ that
>>of modern CPU's. The fact is, modern CPU's tend to need to pre-decode the
>>instruction stream some way, and storing to it while running from it is
>>just a really really bad idea. And since it's so easy to avoid it, you
>>really just shouldn't do it.
>>
> 
> 
> AMD, I believe, has an "annotated" icache

Here is an SMP:

vendor_id	: AuthenticAMD
cpu family	: 6
model		: 6
model name	: AMD Athlon(TM) MP 2000+
stepping	: 2
cpu MHz		: 1680.368
cache size	: 256 KB

empty overhead=11 cycles
load overhead=6 cycles
I$ load overhead=5 cycles
I$ load overhead=6 cycles
I$ store overhead=1051 cycles

-- 
George Anzinger   [e-mail]
High-res-timers:  http://sourceforge.net/projects/high-res-timers/
Preemption patch: http://www.kernel.org/pub/linux/kernel/people/rml