> > > 1. which device is at port address 0xCFB?
> >
> > Hopefully none.
>
> Actually I'm not sure. This code is here since at least 2.0.28,
> and during googling I even found code for direct PCI access
> (http://www-user.tu-chemnitz.de/~heha/viewzip.cgi/hs_freeware/gerald.zip/DIRECTNT.CPP?auto=CPP)
> which sets lowest bit at 0xCFB to 1 before doing PCI config
> accesses and reset it back to original value afterward.
>
> So I believe that there were some chipsets (probably in 486&PCI times)
> which did conf1/conf2 accesses depending on value of this bit.
> Unfortunately I was not able to confirm this - almost nobody provides
> northbridge datasheets from '94 era, even Intel does not provide them
> (f.e. Neptune) anymore :-(
Fortunately that's not true. Grab the relevant docs from:
'ftp://download.intel.com/support/chipsets/430nx/'. The semantics of
0xcf8, 0xcf9, 0xcfa and 0xcfb I/O ports when used as byte quantities is
explained there. Note that 0xcf8 and 0xcfa are the way to get at the PCI
config space using conf2 accesses.
-- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available +- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/