There may be options in your BIOS to disable this "feature". Look
for things like "PCI byte-merging" and/or "PCI read prefetch". I
haven't had access to one of the new SIS based P4 systems yet, so
I don't know how they are setup or exactly how they are violating
the PCI spec. The test will fail either if byte-merging or read
prefetch occurs and perhaps if there is an MTTR covering the memory
mapped region of the chip that is set to write combining mode (I
don't think that the mb() we issue after every memory write helps
in this last case).
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