Re: Intel P6 vs P7 system call performance

Ingo Molnar (mingo@elte.hu)
Sun, 22 Dec 2002 11:23:08 +0100 (CET)

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while reviewing the sysenter trampoline code i started wondering about the
HT case. Dont HT boxes share the MSRs between logical CPUs? This pretty
much breaks the concept of per-logical-CPU sysenter trampolines. It also
makes context-switch time sysenter MSR writing impossible, so i really
hope this is not the case.

Ingo

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