Great!
> > > A paper describing the proposal can be obtained from
> > >
> > > http://www.research.ibm.com/arl/projects/dpm.html
> > >
> > > A working prototype of the proposed framework for
> > > the IBM PowerPC 405LP processor exists and will be made
> > > public in the near future.
> >
> > any idea if/how this will fit into the existing cross platform cpufreq
> > framework ?
>
> It subsumes it, similar to Dominik's ideas in "[RFC] Dynamic Frequency
> and Voltage Scaling Infrastructure" (on the cpufreq list). The idea is
> that you want scaling events to be generated by the kernel rather than
> only scaling on userland input. The paper (and Dominik's mail) give you
> some ideas of when and why...
So, will it basically be a "policy governor" as described in my "[RFC]" mail?
Or does it need other enhancements in the cpufreq core?
BTW, have you noticed the premilinary patch I which implements most of the
DVS infrastructure mentioned in my mail to the cpufreq list yesterday?
Dominik
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