Sure, I'll give you that, but nothing in the architecture is going to
half the size of every pointer for you.
I bet overall the TLB and cache usage is higher. The things the lack
of registers do is spill and thus beat on the stack, big deal, that
all tends to be in a contiguous areas of memory (ie. same cache blocks
and same TLB pages) and at least Intel has optimized stack memory
accesses out the wazoo.
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