Re: NMI handling rework

[Corey Minyard]

Richard B. Johnson wrote:

>On Thu, 7 Nov 2002, Zwane Mwaikambo wrote:
>
>  
>
>>On Thu, 7 Nov 2002, Corey Minyard wrote:
>>
>>    
>>
>>>NMIs cannot be masked, they are by definition non-maskable :-).  You can 
>>>get an NMI while executing an NMI.
>>>      
>>>
>>"After an NMI interrupt is recognized by the P6 family, Pentium, Intel486, 
>>Intel386, and Intel 286 processors, the NMI interrupt is masked until the 
>>first IRET instruction is executed, unlike the 8086 processor."
>>
>>- 18.22.2 NMI Interrupts, Intel IA32 System Developer's Manual vol3d 
>>
Thanks, and thanks to everyone else that pointed this out.

It is still possible, though unlikely, that two NMI sources could occur 
at the same time.  Maybe that's not worth worrying about, and maybe for 
the APICs it works fine.

>>>An NMI-based timer?  I can see the use if you REALLY need accurate 
>>>intervals, but you can't do much in an NMI, no spinlocks, even.
>>>      
>>>
>[SNIPPED...]
>
>You can use a spinlock and, in fact, that's the only way you can
>protect a critical section. The other CPU will spin of course, just
>like the other CPU in a maskable interrupt. That's what spin-locks
>are for. With maskable interrupts, the "cli" affects only the CPU
>that actually fetches that instruction. That's why you need spin-lock
>protection when you have more than one CPU. With NMI, no CPU has
>the effect a "cli" would provide, so they just spin at the lock
>until the lock is released.
>
I should have been more precise here.  You cannot use a spinlock that 
you use outside of the NMI, too.  You might be holding the spinlock when 
the NMI occurs, and you would then be in deadlock.

-Corey