Re: Strange panic as soon as timer interrupts are enabled (recent

[J.E.J. Bottomley]

[e-mail] said:
> Which seems to work, and is similar to what James did, I think. 

Yes, that's almost exactly equivalent.  The voyager start_secondary sequence 
is almost identical to the APIC sequence in function, it just plays with a 
different piece of hardware.

> Not sure that's any less ugly than the above ;-) I prefer your idea of
> moving calibrate_delay, I'll try that sometime soonish, but need to
> stare at what uses the result for a while first. 

The question really is whether the secondaries need to receive any interrupts 
at all (except for the one that booted them) before the smp_commence mask is 
cleared.  I don't believe this to be the case.  calibrate_delay only requires 
that jiffies be ticking, which will happen as long as the boot cpu is 
receiving timer interrupts.  Perhaps the correct fix is not to enable the 
interrupts early in the start_secondary sequence, and not to lower the APIC 
(or VIC in my case) interrupt masks at all until after smp_commence.  Thus the 
boot CPU will handle all the interrupts up until that point.

James