OK I see what you're getting at here -you're talking about the XMC
algorithm.
However, I'm not convinced that we will hit E49 in our specific case - we
looked at this some time ago and felt that because we are not altering
instruction length or boundary, and that even if there is a score-boarding
effect on the register value stored, we still wouldn't generate exceptions
from intermediates. There are apparent inconsistencies in the
architecture manuals; in the past when I've found these and queried the
processor behaviour with Intel's microarchitecture guys they've provided
clarification. I'll do the same here and see what they say. It's no big
deal whatever their response as kernel hooks has two mechanisms: generic,
which is architecturally independent and doesn't use self-modifying code;
and architecturally specific, which does. We can always restrict the IA32
mechanism for processors < P3 to use the generic hook or implement the XMC
algorithm.
Richard
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