Re: Quick aic7xxx bug hunt...

[Justin T. Gibbs]

> Justin T. Gibbs wrote:
>> On some motherboards with some chipsets, you can get these messages if
>> another busmaster (say an IDE drive or a sound card) is hogging the bus.
>> Usually this is with a VIA chipset.  Its not clear why the aic7xxx_old
>> driver would behave differently other than it disables memory write
>> and invalidate PCI transactions on this chip.  The new driver doesn't
>> need that work around.
> 
> 
> Justin,
> 
> One thing I notice is at least one PCI posting bug.  When using MMIO
> (write[bwlq] under Linux), you _must_ use a read[bwlq] to flush the write
> to PCI, if you wish to ensure the write posts at a certain point in the
> code.

> 
> Here is the example PCI posting bug, in ahc_clear_critical_section:
>>                 ahc_outb(ahc, HCNTRL, ahc->unpause);
>>                 do {
>>                         ahc_delay(200);
>>                 } while (!ahc_is_paused(ahc));
> 
> As you can see, there is no read before the udelay(), which is very wrong
> on modern CPUs with write posting...  that's definitely a driver bug that
> will bite you on modern x86 motherboards [and is totally broken on ia64
> and other platforms].
> 
> Please let me know if you have further questions on PCI write posting...

I somewhat doubt that any CPU would hold onto a posted write for 200us
since you are not guaranteed that a read will occur quickly and you want
those write buffers to be availble for other clients, but regardless, the
code has not been as you describe since November of last year.  The
CHANGELOG reads:

                Always perform a bus read prior to waiting in
                a delay loop waiting for a bus write to take
                effect.  This ensures that the first time
                through the loop the delay occurs after the
                write has taken effect.

Of course, the "bug" was benign since the loop does perform a read
so the write is guaranteed to post during the first itteration through
the loop.

--
Justin