Justin,
One thing I notice is at least one PCI posting bug. When using MMIO
(write[bwlq] under Linux), you _must_ use a read[bwlq] to flush the
write to PCI, if you wish to ensure the write posts at a certain point
in the code.
Here is the example PCI posting bug, in ahc_clear_critical_section:
> ahc_outb(ahc, HCNTRL, ahc->unpause);
> do {
> ahc_delay(200);
> } while (!ahc_is_paused(ahc));
As you can see, there is no read before the udelay(), which is very
wrong on modern CPUs with write posting... that's definitely a driver
bug that will bite you on modern x86 motherboards [and is totally broken
on ia64 and other platforms].
Please let me know if you have further questions on PCI write posting...
Jeff
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