On Thu, Sep 19, 2002 at 06:09:34PM -0700, Andrew Morton wrote:
> Can you control the cachability of the memory reads as well?
SSE2 has hints for that (prefetchnti and even prefetcht0,1 etc. for different
cache hierarchies), but it's not completely clear on how much
the CPUs follow these.
For writing it's much more obvious and usually documented even.
See "montdq/movnti", the latter of which even works on register
registers. Ben LaHaise pointed this out to me earlier today.
-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/