I believe you gents are going off at a tangent. Intel's current P4 manual
says the local APIC timer is driven by the "bus clock". For serial APICs
that was doubtless the APIC serial bus clock, which almost always was derived
from the system clock. For P4 systems with the xAPIC in parallel mode, the
only one available is the system bus.
If a multi-node system doesn't have synchronized bus clocks, it doesn't matter
which one you use. The time bases will drift relative to each other.
It's even worse when the "Frequency Spreading" BIOS option is turned on.
Then, the bus clocks are deliberately offset by as much as half a megahertz
(doubtless to pass FCC or equivalent emission certifications).
I don't know what Sun does with the Ultra SPARC 3's time counter. Maybe they
have a separate clock input for it that runs at 1 MHz so skew and
distribution is no problem. That's fine for Sun; they build their own CPUs
and can put in whatever they want. The rest of us have to work with what we
get from the different manufacturers. And, just about all of them use a
value derived from the bus clock -- which might have drift in a multi-node
system.
That's where a better abstraction of the timer hardware would come in handy.
It would use the PIT or TSC for 99% of boxes, and switch to special code for
the weird ones.
--
James Cleverdon
IBM xSeries Linux Solutions
{jamesclv(Unix, preferred), cleverdj(Notes)} at us dot ibm dot com
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