> > I though about that, but what about corner cases where only a single
> > register can be accessed ? (typically alt status). Provide specific
> > routines ? Also, how does the extended addressing works ? by writing
> > several times to the cyl registers ? That would have to be dealt with
> > as well in each host driver then.
>
> There are lots of cases we don't care about speed - things like setup of
> the controller, changing UDMA mode etc.
Erm, think about the state diagram for testing the acceptance and command
migration if TAG is going to be standard.
> Begin a disk write
> Begin a disk read
test command accept/reject
repeat 'til done:
check_status
> PIO transfer in
> PIO transfer out
io hardware atomic segment or burst
(for linus, "atomic" is what is needed to complete, not just linusism")
goto repeat if !done with entire request
The above is where data integrity is lost if error happens.
> End a disk I/O fastpaths (no error case)
>
> Maybe ATAPI command writes ?
>
> beyond that I doubt the rest are critical
There are several other cases, but 95% is the command block execution.
The rest is sense data.
Cheers,
Andre Hedrick
LAD Storage Consulting Group
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