You're the one with a VIA C3 with broken L2 cache?
The "cachesize=0" option will not affect the L2 cache, only
the kernel's reporting of cache size. (Apparently due to some
Tualatins not being able to report correct cache size.)
That C3 is broken and should be replaced. If you really want
to use it, you'll need to hardware-disable the L2 cache. Your
BIOS should have an option for that; if not, try the patch below.
/Mikael
--- linux-2.4.19-pre4/arch/i386/kernel/setup.c.~1~ Sat Mar 23 12:26:01 2002
+++ linux-2.4.19-pre4/arch/i386/kernel/setup.c Sat Mar 23 12:29:17 2002
@@ -1939,6 +1939,7 @@
case 6 ... 8: /* Cyrix III family */
rdmsr (MSR_VIA_FCR, lo, hi);
lo |= (1<<1 | 1<<7); /* Report CX8 & enable PGE */
+ lo |= (1<<8);
wrmsr (MSR_VIA_FCR, lo, hi);
set_bit(X86_FEATURE_CX8, &c->x86_capability);
-
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