Re: [Lse-tech] Re: 10.31 second kernel compile

On Sat, Mar 16, 2002 at 12:02:59PM -0800, Linus Torvalds wrote:
> 
> On Sat, 16 Mar 2002 [e-mail] wrote:
> > On Sat, Mar 16, 2002 at 11:16:16AM -0800, Linus Torvalds wrote:
> > > Show me a semi-sane architecture that _matters_ from a commercial angle.
> > 
> > I thought we were into this for the pure technical thrill-)
> 
> I don't know about you, but to me the difference between technological
> thrill and masturbation is that real technology actually matters to real
> people.

Beyond me. Some kind of sophisticated California thing that us
poor folks in New Mexico can hardly imagine, I suppose. 

> 
> I'm not in it for some theoretical good. I want my code to make _sense_.
> 
> > > page tables. And I personally like how Hammer looks more than the ia64 VM 
> > > horror.
> > 
> > No kidding. But  I want TLB load instructions. 
> 
> TLB load instructions + hardware walking just do not make much sense if 
> you allow the loaded entries to be victimized.

If you have TLB load, you can sabotage hw walking and at least see whether
you can beat it. I think it could be done, because the OS could adapt to
the characteristics of the process - using perhaps on mm layout for 
kde applets and a different one for oracle ...

> Of course, you can have a separate "lock this TLB entry that I give you" 
> thing, which can be useful for real-time, and can also be useful for 
> having per-CPU data areas. 
> 
> But then you might as well consider that a BAT register ("block address 
> translation", ppc has those too), and separate from the TLB.

Bats are a good start. What I'd like is also a "small unpaged
process base/limit" set of registers or two.

---------------------------------------------------------
Victor Yodaiken 
Finite State Machine Labs: The RTLinux Company.
 www.fsmlabs.com  www.rtlinux.com