Re: [Lse-tech] Re: 10.31 second kernel compile

yodaiken@fsmlabs.com
Sat, 16 Mar 2002 13:08:06 -0700

On Sat, Mar 16, 2002 at 11:58:22AM -0800, Linus Torvalds wrote:
> This implies that the TLB should be split into a L1 and a L2, for all
> the same reasons you split other caches that way (and with the L1
> probably being duplicated among all memory units)

AMD claims L1, L2 and with hammer an
I/D split as well. But no TLB load instruction as
far as I can tell

-- 
---------------------------------------------------------
Victor Yodaiken 
Finite State Machine Labs: The RTLinux Company.
 www.fsmlabs.com  www.rtlinux.com


-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/