Re: Severe IRQ problems on Foster (P4 Xeon) system

[Bill Davidsen]

On Wed, 13 Mar 2002, Ingo Molnar wrote:

> 
> On Wed, 13 Mar 2002, Martin Wilck wrote:
> 
> > First of all, we see that virtually 100% of all IRQs are handled by
> > CPU 0. I have seen this reported a number of times before. I guess it
> > can become a severe performance problem in IRQ-intensive situations.
> 
> i've written a patch for this, it's enclosed in this email. It implements
> a brownean motion of IRQs, based on load patterns. The concept works
> really well on Foster CPUs - eg. it will redirect IRQs to idle CPUs - but
> if all CPUs are idle then the IRQs are randomly and evenly distributed
> between CPUs.

If several processors are idle, say CPU0 busy and CPU[123] idle, does it
preferentially use a "CPU" on another chip? And does that make any
difference? It's not clear to me if the HT CPUs share cache or not, they
obviously share bandwidth from L2 to RAM.

I'm looking at P4 chips and boards, my 2Q02 budget has some $$ for a
system. I also will be getting some laptops 3Q02, does the new P4-M mobile
chip by any chance have HT? If so a good reason to go Intel, assuming that
either the BIOS or Linux can get it to use the feature ;-)

-- 
bill davidsen <[e-mail]>
  CTO, TMR Associates, Inc
Doing interesting things with little computers since 1979.