Re: [PATCH] Support for assymmetric SMP

[Kurt Garloff]

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Hi Andrea,

On Mon, Mar 11, 2002 at 05:29:54AM +0100, Andrea Arcangeli wrote:
> the only problem is if you happen to get the timer irq always in the
> same cpu for a few seconds, then the last_tsc_low will wrap around and
> gettimeofday will be wrong. And even if you snapshot the full 64bit of the
> tsc you'll run into some trouble if the timer irq will be delivered only
> to the same cpu for a long time (for example if you use irq bindings).
> you'd lose precision and you'll run into the measuration errors of
> fast_gettimeoffset_quotient. The right support for asynchronous TSC
> handling is a bit more complicated unfortunately.

If your APIC works, your CPUs should get the timer IRQs in alternating orde=
r.
At least that is what seems to happen on the SMP box where I created and
tested this patch. It works perfectly there.

In the more general case, you may need to do more, right.
You could make the xtime global again and send IPIs for every timer
interrupt to make all CPUs update their TSC offset.
Storing the full 64bit TSC may be a good option though.

So, if people wanted to have this included I'd rather document the
limitations (don't bind the timer IRQ to one CPU) than introducing
complexity which may hurt the normal SMP user.

Regards,
--=20
Kurt Garloff  <[e-mail]>                          Eindhoven, NL
GPG key: See mail header, key servers         Linux kernel development
SuSE Linux AG, Nuernberg, DE                            SCSI, Security

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