Re: [Lse-tech] NUMA scheduling

[Timothy D. Witham]

On Mon, 2002-02-25 at 11:03, Larry McVoy wrote:
 Snip
> 
> If you read the early hardware papers on SMP, they all claim "Symmetric
> Multi Processor", i.e., you can run any process on any CPU.  Skip forward
> 3 years, now read the cache affinity papers from the same hardware people.
> You have to step back and squint but what you'll see is that these papers
> could be summarized on one sentence:
> 
> 	"Oops, we lied, it's not really symmetric at all"
> 

  In the interests of historical accuracy.  It was a case of underlying
technology changes.  The original research was done with processors
with 8k caches (total) with the processors external and
internal bus speeds being the same and those equal to the backplane
bus speed.  Shift forward 4 years and you had 512 KB external caches,
and a ratio of the difference between the external processor cache
and main memory of over 20x.  This resulted in a very different 
set of optimizations resulting in the cache affinity schedulers. 

Tim
 
processor boards with 512K caches.  In  
> You should treat each CPU as a mini system and think of a process reschedule
> someplace else as a checkpoint/restart and assume that is heavy weight.  In
> fact, I'd love to see the scheduler code forcibly sleep the process for 
> 500 milliseconds each time it lands on a different CPU.  Tune the system
> to work well with that, then take out the sleep, and you'll have the right
> answer.
> -- 
> ---
> Larry McVoy            	 lm at bitmover.com           http://www.bitmover.com/lm 
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-- 
Timothy D. Witham - Lab Director - [e-mail]
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