I suppose you're talking about the Intel patch, not mine, which is
obviously out. I admit it was too complex.
The problem with the original code is that it combines reading the status
of the MTRR default register and disabling cache in a single step that
is performed simultaneously by all CPUs.
The patch from Intel inserts synchronization between these two steps,
thereby avoiding that the second CPU reads a "defaults status" that in
reality is the "cache disabled" status the first CPU had set before.
This suffices to fix the problem.
Martin
-- Martin Wilck Phone: +49 5251 8 15113 Fujitsu Siemens Computers Fax: +49 5251 8 20409 Heinz-Nixdorf-Ring 1 mailto:Martin.Wilck@Fujitsu-Siemens.com D-33106 Paderborn http://www.fujitsu-siemens.com/primergy
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