> I am working on a project that keep accessing lots of memory
> randomly(say 500MB-1.5GB) and we do have such amount of memory
> installed so there's almost no page faults while running the entire
> program. Since x86 architecutre has a 4M page feature, is it possible
> to make use of these big pages instead of 4K pages in my program (a
> user-level application) so I can expect much fewer TLB misses due to
> the reduced number of TLB entries?
This isn't currently implemented, still somewhere on the TODO list ;/
Rik
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