unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x00);
That assumes atapi_reg will be 0x24 beyond the base of bar4 (high_16).
Is my PCI code showing me an incorrect size for bar4, or is this
accessing registers beyond its limits?
Thanks.
Gerald
Andre Hedrick wrote:
> I fixed that problem after it was discovered.
> It is in the newest drivers.
>
>
> On Wed, 16 Jan 2002, Gerald Champagne wrote:
>
>
>>I thought I understood the way PCI devices are accessed in Linux,
>>but the code for the Promise PCI controllers has me confused. To
>>me it looks like the code is accessing registers outside the area
>>allocated to the PCI device during initialization.
>>
>>The device is configured with the following resources (on a Mips-based
>>platform):
>>
>>00:08.0 Class 0180: 105a:4d68 (rev 01)
>> I/O at 0x00000080 [size=0x8]
>> I/O at 0x00000088 [size=0x4]
>> I/O at 0x00000090 [size=0x8]
>> I/O at 0x00000098 [size=0x4]
>> I/O at 0x000000a0 [size=0x10]
>> Mem at 0x08004000 [size=0x4000]
>>
>>The Promise code uses registers specified using bar4 but it uses offsets
>>above 0x0f. Here's an example of the code in drivers/ide/pdc202xx.c:
>>
>>void pdc202xx_reset (ide_drive_t *drive)
>>{
>> unsigned long high_16 = pci_resource_start(HWIF(drive)->pci_dev, 4);
>> byte udma_speed_flag = inb(high_16 + 0x001f);
>>
>> OUT_BYTE(udma_speed_flag | 0x10, high_16 + 0x001f);
>> mdelay(100);
>> OUT_BYTE(udma_speed_flag & ~0x10, high_16 + 0x001f);
>> mdelay(2000); /* 2 seconds ?! */
>>}
>>
>>How can the code above try to write to a register 0x1f into a region with
>>a size of 0x10? Wouldn't that stomp on the registers of some other PCI device?
>>
>>Thanks.
>>
>>Gerald
>>
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