KT133 PCI implementation, possibly applying to other VIA chipsets too.
Master memory reads can talk 45 cycles rather than 16 (the max defined
in the PCI spec) - this sounds like it could be due to either a) bad
motherboard design with signal problems, or b) BIOS chipset
configuration (try setting 'PCI master read caching' to on?). This is
since problems have been reported with different make motherboards using
the same chipset, and those being the only two factors differing.
Of course, this may well not help if it is geniunely a bug in the
kernel, but may solve the PCI corruption (if any).
Also, if it is a chipset issue, updating the BIOS can help at times,
with the vendor incorporating work-arounds for known chipset problems
(eg the well-publicised IDE corruption issue).
Dan
___________________
Daniel J Blueman
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