All the studies I saw were back from the days when
cache-speed/expensive-memory-speed was close to 1. In this case, the
effect of randomizing memory fetches is no big deal. The rest
of standard PPC mmu architecture is pretty nice, but, if the Alpha
architects could decide to use the PC cmos clock as their only
prgrammable timer, and the Itanium guys could decide to put in a single
shift-mask path, why shouldn't the IBM designers get to destroy cache
by wasting a bunch of CPU area logic?
-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/