Re: [PATCH] Pentium IV cacheline size.

Mark Hahn (hahn@physics.mcmaster.ca)
Sat, 13 Oct 2001 12:31:04 -0400 (EDT)

> Currently, we're using a L1_CACHE_SHIFT value of 7
> for Pentium 4, which equates to 128 byte cache lines.
> Curious, I dumped the info on the only P4 I could find,
> and noticed they were 64 byte.

the value is correct, but the name should be SMP rather than L1,
since we (only?) use the value for aligning data to avoid false sharing.

regards, mark hahn

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