Lets put an actual load example (which I just happen do be doing now):
On my 2x366 celeron smp box, I have a kernel compile running (-j15), and a
bzip2 compressing several large files...
Right now, (2.4.10-ac4, compiling 2.4.10-ac10+preempt) both of my L2
processor caches are moot (128KB) because of the several gcc processes
running, and the very loose affinity.
In this case, bzip2 should probably get a processor (CPU0) to itself, and my kernel
compile another(CPU1).
It would be interesting to see how a system that has a kind of hierarchy to
the processors. All new processes would always start on cpu0, and long
running processes would get slowly moved up the list of processors the
longer they run. Thus, CPU0 would have abysmal L2 cache locality, and CPU7
would have the best caching possible with its L2.
What do you guys think?
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