Re: [SOLVED + PATCH]: documented Oops running big-endian reiserfs on parisc architecture

[Richard B. Johnson]

On Tue, 4 Sep 2001, Ulrich Weigand wrote:
[SNIPPED...]

> 
> If these instructions really *need* to be atomic, then reiserfs should
> ensure they are performed on properly aligned data, or else there might
> be subtle bugs even on Intel, because the operations will not actually
> be atomic (even though they don't trap).
>

Regardless of alignment, locked instructions in Intel machines are
atomic. Any "hidden" read/modify/write operations are performed
by the hardware, under the lock, preventing access by any other
CPUs or DMA.
 
> If you say that reiserfs doesn't really need these operations to be
> atomic because they run under other locks anyway, then they should not
> be using atomic operations in the first place; this will only cause
> unnecessary slowdown even on Intel.
> 

Agreed that there are many "atomic_t" types on some drivers, and
"atomic" operations that don't need to be there. Unless a DMA operation
is in progress, anything executing under a spin-lock doesn't need
to be an "atomic" operation to make it, truly, atomic.

Cheers,
Dick Johnson

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