Re: eepro100 (PCI ID 82820) lockups/failure

[Richard B. Johnson]

On Mon, 6 Aug 2001, Colin Walters wrote:

> Andrey Savochkin <[e-mail]> writes:
> 
> > Someone who experiences such timeouts needs to figure out how much
> > time it really can take before a command is accepted.  Some time ago
> > the timeout was increased by the factor of 10, and now the current
> > timeout looks being insufficient.  It might be a problem with the
> > time of specific commands or specific chip revisions.  Or some
> > hardware is too clever and somehow optimizes those repeated read
> > operations, so that they no longer take a fixed number of bus
> > cycles.
> 
[SNIPPED...]

This may not be a timing problem, but rather a problem that was
attempted to be fixed with some timing change.

Possible problem (and solution). Given:

	writel(value, pci_reg);
	status = readl(pci_reg);

The second readl() may (read will) complete before the writel().
This is because writes to the PCI bus may be posted (queued). The
first read will force all writes to complete, however the value
read may be something that was not yet affected by the write.

	writel(value, pci_reg);
	status = readl(pci_reg);
	status = readl(pci_reg);

Would fix, but gcc may "optimize" one of these away, therefore I
suggest reading something, within the boards address space that
is never used, i.e., some offset that gives the model number or
something. It must actually respond to a read because otherwise
performance will degrade while waiting for the PCI bus error.

Cheers,
Dick Johnson

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