Re: PCI bus speed

[Richard B. Johnson]

On Fri, 3 Aug 2001, Tim Hockin wrote:

> > yes. I see some items with flags listed as:
> > 	Flags: bus master, 66Mhz, medium devsel, latency 64, IRQ 10    
> 
> I think that reflects the '66 MHz CAPABLE' bit.  That means that IFF every
> device on the segment and IFF the bridge ALL can run at 66MHz, you MIGHT be
> at 66 MHz.  Or anywhere between 33 and 66, or for that matter, less than
> 33.
> 
> Tim

Yes, sort-of.  Bit 5 in the status register is supposed to be
"hard-wired by designer" according to the 2.2 spec. It is
TRUE if the board is capable of running at 66MHz.

However, some boards reflect the state of the bus 66MHz capable
bit. Any board that is not 66MHz capable must pull this bit to
ground (logic low). This will automatically switch a 66MHz bus
to 33MHz, usually by changing a divisor in a clock-chip.

This makes certain that any board that is not 66MHz capable will
force the bus to run at 33MHz. However, it might ALSO make any
status, bit 5  in other devices "strangely" show that they are
not 66MHz capable anymore. IOW, if I have all 66MHz devices on my
bus, and add a new board, suddenly __none__ of the devices appear
66MHz, capable. It's hard to find out the culprit without removing
boards one-at-a-time.

Cheers,
Dick Johnson

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