Re: Memory Write Ordering Question

[Richard B. Johnson]

On Wed, 1 Aug 2001, James W. Lake wrote:

> 
> Hello,
> 
> I've run into a problem with memory write ordering on a PCI Device.  
> 
> The  card has 2 memory regions, pthis->pConfigMem (PCI Chip
> Configuration), and pthis->pDspMem (A DSP's memory on the PCI Card)
> 
> The code sequence below doesn't work out as expected.  The
> writel(temp,addr); at the bottom actually occurs in the middle of the
> memcpy_toio() operation.
[SNIPPED...]

A PCI bus master will defer writes until its cache gets full or
a read is requested. You can force the pending writes to complete
with any read. You can also configure some devices to not defer writes
(Cache-line Size register).

This "bursting" is a characteristic of PCI masters which allows
them to transfer data in groups of long-words, typically up to
16 long-words at a time.

If you need PCI access to be atomic, without disabling its cache
which slows down access, do a dummy read from anywhere within the
device address space, at places where you must guarantee that
previous data were written (like when configuring registers).

Sometimes the reads don't have to be 'dummy' sometimes you can
reorder device configuration transactions so that the required
result is achieved.

Also, make sure that you use ioremap_nocache() when setting up
access to the device. That solves another cache problem where
some reads may be read from memory rather than even accessing
the PCI bus.

Cheers,
Dick Johnson

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