Re: VIA KT133A / athlon / MMX

[Kurt Garloff]

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Hi Michael,

thanks for your comments!

On Mon, Jul 30, 2001 at 03:15:38PM +0100, Michael wrote:
> > > On Sun, 29 Jul 2001 22:28:30 +0200, Kurt Garloff wrote:
> > > [54:6]=3DProbe Next Tag State T1	0=3Ddisable   1=3Denable
> >=20
> > Main suspect. (Should be 0)
>=20
> That's set in my stable kt133a system.

But did you experience problems at all with your kernel when compiled for
K7? Note that most (if not all) systems seem to work stable with K6 or PPro
optimized kernels.

> > > [54:0]=3DFast Write-to-Read	0=3Ddisable   1=3Denable
> >=20
> > Third candidate. (Should be 0)
>=20
> as is this one.
> =20
> > > [68:2]=3DBurst Refresh(4 times)	0=3Ddisable   1=3Denable
> >=20
> > Fourth candidate (Should be 0?)
>=20
> I set this one yesterday to see if it would trigger the problem, it
> didn't :o/ Same with a few differences between my system and 0x6b, which
> didn't either.
>=20
> Out of curiosity, where are you getting the 'should be 0/1' details from?

Comparing the lspci -vxxx output of working and non-working systems.

You did no comment on the second candidate:

> [68:4]=3DDRAM Data Latch Delay  0=3DLatch     1=3DDelay latch

Second candidate (Should be 1)

Regards,
--=20
Kurt Garloff  <[e-mail]>                          Eindhoven, NL
GPG key: See mail header, key servers         Linux kernel development
SuSE GmbH, Nuernberg, DE                                SCSI, Security

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