RE: Sticky IO-APIC problem

[Colin Bayer]

'K, after hours (which seemed like years) of surfing the datasheets of the 82810AA ICH (I/O Controller Hub) from Intel, I've come up with step-by-step hardware-level instructions for enabling the IO-APIC with pre-defined PIRQs (I'm not an assembly guru, so I can't help with the coding of this):

1) Set bit 7 of register PIRQ[n]_ROUT (offset 60h) to 0.
2) Set bits 3:0 of the same register to the (8259) interrupt to be mapped on this PIRQ (big-endian).
3) Set the corresponding bit on the correct 8259s (master is at 21h, slave at A1h) OCW1 register to mask the interrupt; the way I read it, bit 7 of the A1h register is IRQ 15, bit 0 of 21h is IRQ 0.
4) Set bit 8 of GEN_CNTL (starting offset D0h, hehe...) to 1 to enable the I/O APIC.

Anyway, that's as far as I could read into the process.  Hope somebody out there in maintainer-land can create a cogent snippet of code out of it.  If such code exists, plz don't flame me...

     -- Colin

On the first day, man created the computer.  On the second day, God proclaimed from the heavens, "F0 0F C7 C8".

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