> Basically if you know the L2 cache size and the assosciativity you can
> do this as long as you can get a "2 * L2 cache size * assosciativity"
> piece of contiguous physical memory. When you need this "simon says"
> flush, you basically read this physical memory span and this will
> guarentee that all dirty data has exited the L2 cache.
Fine. So it should be possible to do it on all architectures with
physically-indexed caches - that's good. Architectures with
virtually-indexed caches are going to have explicit cache management
functionality anyway, presumably :)
Obviously the algorithm you describe should not be implemented in
arch-independent drivers. It should be in include/asm-*, for those
architectures which _can't_ do it with a single cache management instruction
(or loop of same).
What shall we call this function? The intuitive "flush_dcache_range" appears
to have already been taken.
-- dwmw2
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