Re: SMP on assym. x86

[Eric W. Biederman]

Kurt Garloff <[e-mail]> writes:

> On Wed, Mar 21, 2001 at 11:41:33PM +0000, Alan Cox wrote:
> > > > handle the situation with 2 different CPUs (AMP = Assymmetric
> > > > multiprocessing ;-) correctly.
> > > 
> > > "correctly".  Intel doesn't support this (mis)configuration:
> > > especially with different steppings, not to mention models.
> 
> I wouldn't call it misconfiguration, just because it's a bit more difficult
> to handle.
> On the iontel side: You should watch out for matching APICs, voltages and
> cache coherency (MESI) protocol. Actually, Deschutes and Coppermine just
> work fine in spite of slightly different voltage.

The spooky thing is if there is that it may work just fine most of the
time but the differences between the CPU's might cause very strange
behavior every once in a great while.  Which is a hardware argument, for
why you shouldn't trust such a configuration.

However it is still worth some thought.  The hardware argument gets much
weaker when you have something like dual AMD's.  The reason is that
with a point to point bus you may actually be able to sanely support
multiple cpu revs and speeds without even any theoretical hardware consequences.

And NUMA machines make this argument even stronger.

However I would suggest that we build some good kernel->kernel apis
for dealing with kernels with a wicked fast interconnect.  And then
for NUMA and for the other cases where it really matters we can run multiple
kernels, and the mismatch problems just drop away.

Eric